Sciweavers

138 search results - page 25 / 28
» Functional test generation for delay faults in combinational...
Sort
View
SEDE
2007
13 years 9 months ago
Case study: A tool centric approach for fault avoidance in microchip designs
— Achieving reliability in fault tolerant systems requires both avoidance and redundancy. This study focuses on avoidance as it pertains to the design of microchips. The lifecycl...
Clemente Izurieta
DAC
2006
ACM
13 years 9 months ago
Systematic software-based self-test for pipelined processors
Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving ...
Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis H...
DATE
2008
IEEE
89views Hardware» more  DATE 2008»
14 years 2 months ago
EPIC: Ending Piracy of Integrated Circuits
As semiconductor manufacturing requires greater capital investments, the use of contract foundries has grown dramatically, increasing exposure to mask theft and unauthorized exces...
Jarrod A. Roy, Farinaz Koushanfar, Igor L. Markov
ISCAS
2006
IEEE
103views Hardware» more  ISCAS 2006»
14 years 1 months ago
A neural model for sonar-based navigation in obstacle fields
— The rapid control of sonar-guided vehicles through obstacle fields has been a goal of robotics for decades. How sensory data is represented strongly affects how obstacles and g...
Timothy K. Horiuchi
DAC
2003
ACM
14 years 8 months ago
A scalable software-based self-test methodology for programmable processors
Software-based self-test (SBST) is an emerging approach to address the challenges of high-quality, at-speed test for complex programmable processors and systems-on chips (SoCs) th...
Li Chen, Srivaths Ravi, Anand Raghunathan, Sujit D...