138 search results - page 7 / 28 » Functional test generation for delay faults in combinational... |
VLSID
1996
IEEE
13 years 12 months ago
1996
IEEE
W epropose a coverage metric and a two-pass test generation method for path delay faults in combinational logic circuits. The coverage is measured for each line with a rising and ...
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
- Under manufacturing process variation, a path through a fault site is called longest for delay test if there exists a process condition under which the path has the maximum delay...
ETS
2009
IEEE
2009
IEEE
Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques
13 years 5 months ago
Due to the increased speed in modern designs, testing for delay faults has become an important issue in the postproduction test of manufactured chips. A high fault coverage is nee...
EURODAC
1994
IEEE
13 years 11 months ago
1994
IEEE
This paper presents Resist, a recursive test pattern generation (TPG) algorithm for path delay fault testing of scan-based circuits. In contrast to other approaches, it exploits t...
VTS
2003
IEEE
14 years 28 days ago
2003
IEEE
Delay faults are an increasingly important test challenge. Traditional open and bridge fault models are incomplete because only the functional fault or a subset of delay fault are...