138 search results - page 9 / 28 » Functional test generation for delay faults in combinational... |
EURODAC
1995
IEEE
13 years 11 months ago
1995
IEEE
We examine delay models used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which signi cantly a ect the actual...
DATE
2003
IEEE
14 years 29 days ago
2003
IEEE
DAC
1994
ACM
13 years 11 months ago
1994
ACM
Recent results indicate that functional test pattern generation (TPG) techniques may provide better defect coverages than do traditional logic-level techniques. Functional TPG alg...
TCAD
2002
13 years 7 months ago
2002
A test pattern generator (TPG) for built-in self-test (BIST), which can reduce switching activity during test application, is proposed. The proposed TPG, called dual-speed LFSR (DS...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
This paper addresses the run-time diagnosis of delay faults in functional units of microprocessors. Despite the popularity of the stuck-at fault model, it is no longer the only re...