694 search results - page 25 / 139 » Gate Sizing Using a Statistical Delay Model |
DAC
2008
ACM
14 years 8 months ago
2008
ACM
Current source based cell models are becoming a necessity for accurate timing and noise analysis at 65nm and below. Voltage waveform shapes are increasingly more difficult to repr...
DAC
1999
ACM
14 years 8 months ago
1999
ACM
We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only th...
IJCNN
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract— Prediction of natural gas consumption is an important element in gas load management aimed to better utilize the facilities of a gas distribution system. The major chal...
ISPD
1998
ACM
13 years 11 months ago
1998
ACM
We describe a novel iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. Our new approach is considerably faster than p...
IOLTS
2006
IEEE
14 years 1 months ago
2006
IEEE
— Delay failures are becoming a dominant failure mechanism in nanometer technologies. Diagnosis of such failures is important to ensure yield and robustness of the design. Howeve...