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» Gate Sizing Using a Statistical Delay Model
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ICCAD
1997
IEEE
122views Hardware» more  ICCAD 1997»
14 years 1 months ago
Approximate timing analysis of combinational circuits under the XBD0 model
This paper is concerned with approximate delay computation algorithms for combinational circuits. As a result of intensive research in the early 90’s [3, 8] efficient tools exi...
Yuji Kukimoto, Wilsin Gosti, Alexander Saldanha, R...
ASPDAC
2009
ACM
161views Hardware» more  ASPDAC 2009»
14 years 3 months ago
Risk aversion min-period retiming under process variations
— Recent advances in statistical timing analysis (SSTA) achieve great success in computing arrival times under variations by extending sum and maximum operations to random variab...
Jia Wang, Hai Zhou
ICCAD
1998
IEEE
105views Hardware» more  ICCAD 1998»
14 years 1 months ago
Fanout optimization under a submicron transistor-level delay model
In this paper we present a new fanout optimization algorithm which is particularly suitable for digital circuits designed with submicron CMOS technologies. Restricting the class o...
Pasquale Cocchini, Massoud Pedram, Gianluca Piccin...
ADHOC
2005
119views more  ADHOC 2005»
13 years 9 months ago
A link-indexed statistical traffic prediction approach to improving IEEE 802.11 PSM
Power management is an important technique to prolong the lifetime of battery-powered wireless ad hoc networks. The fact that the energy consumed in the idle state dominates the t...
Chunyu Hu, Jennifer C. Hou
DAC
1998
ACM
14 years 10 months ago
Maximum Power Estimation Using the Limiting Distributions of Extreme Order Statistics
In this paper we present a statistical method for estimating the maximum power consumption in VLSI circuits. The method is based on the theory of extreme order statistics applied ...
Qinru Qiu, Qing Wu, Massoud Pedram