694 search results - page 6 / 139 » Gate Sizing Using a Statistical Delay Model |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract— Continuing scaling of CMOS technology has allowed aggressive pursuant of increased clock rate in DSM chips. The ever shorter clock period has made switching times of di...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
— In this paper, we approach the gate sizing problem in VLSI circuits in the context of increasing variability of process and circuit parameters as technology scales into the nan...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
FinFET devices promise to replace traditional MOSFETs because of superior ability in controlling leakage and minimizing short channel effects while delivering a strong drive curre...
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
With an ever-increasing portion of the delay in highspeed CMOS chips attributable to the interconnect, interconnect-circuit design automation continues to grow in importance. By t...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...