36 search results - page 1 / 8 » Gate sizing for large cell-based designs |
DATE
2009
IEEE
14 years 5 months ago
2009
IEEE
—Today, many chips are designed with predefined discrete cell libraries. In this paper we present a new fast gate sizing algorithm that works natively with discrete cell choices...
DAC
2007
ACM
14 years 12 months ago
2007
ACM
With increasing time-to-market pressure and shortening semiconductor product cycles, more and more chips are being designed with library-based methodologies. In spite of this shif...
ICCAD
2004
IEEE
14 years 7 months ago
2004
IEEE
Abstract— This paper presents a post-route, timingconstrained gate-sizing algorithm for crosstalk reduction. Gate-sizing has emerged as a practical and feasible method to reduce ...
ISPD
2009
ACM
14 years 5 months ago
2009
ACM
Gate sizing and threshold voltage (Vt) assignment are popular techniques for circuit timing and power optimization. Existing methods, by and large, are either sensitivity-driven h...
ITC
1992
IEEE
14 years 3 months ago
1992
IEEE
In this paper we report an automatic test pattern generator that can handle designs with one million gates or more on medium size workstations. Run times and success rates, i.e. t...