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ICCAD
2002
IEEE
80views Hardware» more  ICCAD 2002»
14 years 4 months ago
Minimizing power across multiple technology and design levels
Approaches to achieve low-power and high-speed VLSI's are described with the emphasis on techniques across multiple technology and design levels. To suppress the leakage curr...
Takayasu Sakurai
DFT
2009
IEEE
127views VLSI» more  DFT 2009»
14 years 2 months ago
A Sensor to Detect Normal or Reverse Temperature Dependence in Nanoscale CMOS Circuits
The temperature dependence of MOSFET drain current varies with supply voltage. Two distinct voltage regions exist—a normal dependence (ND) region where an increase in temperatur...
David Wolpert, Paul Ampadu
ASPDAC
2009
ACM
143views Hardware» more  ASPDAC 2009»
14 years 2 months ago
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method
In this paper, we present a novel statistical full-chip leakage power analysis method. The new method can provide a general framework to derive the full-chip leakage current or po...
Ruijing Shen, Ning Mi, Sheldon X.-D. Tan, Yici Cai...
ISCAS
2007
IEEE
90views Hardware» more  ISCAS 2007»
14 years 1 months ago
Leakage-Aware Design of Nanometer SoC
– In the sub-65 nm CMOS technologies, subthreshold and gate dielectric leakage currents need to be simultaneously suppressed for effective energy reduction. New low-leakage circu...
Volkan Kursun, Sherif A. Tawfik, Zhiyu Liu
STOC
1998
ACM
112views Algorithms» more  STOC 1998»
13 years 11 months ago
Quantum Circuits with Mixed States
Current formal models for quantum computation deal only with unitary gates operating on “pure quantum states”. In these models it is difficult or impossible to deal formally w...
Dorit Aharonov, Alexei Kitaev, Noam Nisan