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DAC
2004
ACM
14 years 8 months ago
Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining
With deep-sub-micron (DSM) technology, statistical timing analysis becomes increasingly crucial to characterize signal transmission over global interconnect wires. In this paper, ...
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
DAC
2006
ACM
14 years 8 months ago
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Ruten...
DAC
2006
ACM
14 years 8 months ago
Criticality computation in parameterized statistical timing
Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult ...
Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswa...
STOC
2009
ACM
155views Algorithms» more  STOC 2009»
14 years 8 months ago
A nearly optimal oracle for avoiding failed vertices and edges
We present an improved oracle for the distance sensitivity problem. The goal is to preprocess a directed graph G = (V, E) with non-negative edge weights to answer queries of the f...
Aaron Bernstein, David R. Karger
EUROGRAPHICS
2010
Eurographics
14 years 4 months ago
Uncertain 2D Vector Field Topology
We introduce an approach to visualize stationary 2D vector fields with global uncertainty obtained by considering the transport of local uncertainty in the flow. For this, we ex...
Mathias Otto, Tobias Germer, Hans-Christian Hege, ...