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AOSD
2009
ACM
14 years 3 months ago
Modelling hardware verification concerns specified in the e language: an experience report
e is an aspect-oriented hardware verification language that is widely used to verify the design of electronic circuits through the development and execution of testbenches. In rec...
Darren Galpin, Cormac Driver, Siobhán Clark...
DATE
2005
IEEE
115views Hardware» more  DATE 2005»
14 years 2 months ago
Functional Coverage Driven Test Generation for Validation of Pipelined Processors
Functional verification of microprocessors is one of the most complex and expensive tasks in the current system-on-chip design process. A significant bottleneck in the validatio...
Prabhat Mishra, Nikil D. Dutt
SRDS
2003
IEEE
14 years 1 months ago
Transparent Fault-Tolerant Java Virtual Machine
Replication is one of the prominent approaches for obtaining fault tolerance. Implementing replication on commodity hardware and in a transparent fashion, i.e., without changing t...
Roy Friedman, Alon Kama
DATE
2007
IEEE
98views Hardware» more  DATE 2007»
14 years 2 months ago
Simulation-based reusable posynomial models for MOS transistor parameters
We present an algorithm to automatically design posynomial models for parameters of the MOS transistors using simulation data. These models improve the accuracy of the Geometric P...
Varun Aggarwal, Una-May O'Reilly
RTAS
2008
IEEE
14 years 2 months ago
Real-Time Distributed Discrete-Event Execution with Fault Tolerance
We build on PTIDES, a programming model for distributed embedded systems that uses discrete-event (DE) models as program specifications. PTIDES improves on distributed DE executi...
Thomas Huining Feng, Edward A. Lee