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» Glitch Analysis and Reduction in Register Transfer Level
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FPGA
2007
ACM
124views FPGA» more  FPGA 2007»
13 years 11 months ago
Efficient hardware checkpointing: concepts, overhead analysis, and implementation
Progress in reconfigurable hardware technology allows the implementation of complete SoCs in today's FPGAs. In the context design for reliability, software checkpointing is a...
Dirk Koch, Christian Haubelt, Jürgen Teich
ISLPED
1995
ACM
131views Hardware» more  ISLPED 1995»
13 years 11 months ago
Guarded evaluation: pushing power management to logic synthesis/design
The need to reduce the power consumption of the next generation of digital systems is clearly recognized. At the system level, power management is a very powerful technique and de...
Vivek Tiwari, Sharad Malik, Pranav Ashar
DAC
2005
ACM
14 years 8 months ago
MiniBit: bit-width optimization via affine arithmetic
MiniBit, our automated approach for optimizing bit-widths of fixed-point designs is based on static analysis via affine arithmetic. We describe methods to minimize both the intege...
Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayn...
DAC
2004
ACM
14 years 8 months ago
Circuit-aware architectural simulation
Architectural simulation has achieved a prominent role in the system design cycle by providing designers the ability to quickly examine a wide variety of design choices. However, ...
Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Tod...
DATE
2006
IEEE
113views Hardware» more  DATE 2006»
14 years 1 months ago
Automatic ADL-based operand isolation for embedded processors
Cutting-edge applications of future embedded systems demand highest processor performance with low power consumption to get acceptable battery-life times. Therefore, low power opt...
Anupam Chattopadhyay, B. Geukes, David Kammler, Er...