403 search results - page 60 / 81 » Gradient clock synchronization |
ICCAD
2003
IEEE
14 years 5 months ago
2003
IEEE
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous design, this requires the consideration o...
ICCAD
2005
IEEE
14 years 2 months ago
2005
IEEE
— This paper presents an architecture and a wrapper synthesis approach for the design of multi-clock systems-on-chips. We build upon the initial work on multi-clock latency-insen...
ISLPED
2004
ACM
14 years 2 months ago
2004
ACM
As clock frequency and die area increase, achieving energy efficiency, while distributing a low skew, global clock signal becomes increasingly difficult. Challenges imposed by dee...
ASYNC
2003
IEEE
14 years 1 months ago
2003
IEEE
High-speed asynchronous ripple FIFOs may be easily embedded in synchronous environments and can elegantly handle the problem of forwarding data between clock domains. In cases whe...
SRDS
2000
IEEE
14 years 1 months ago
2000
IEEE
Validation of distributed systems using fault injection is difficult because of their inherent complexity, lack of a global clock, and lack of an easily accessible notion of a gl...