9 search results - page 1 / 2 » Guaranteeing performance yield in high-level synthesis |
DATE
2008
IEEE
14 years 5 months ago
2008
IEEE
— The worst-case delay/power of function units has been used in traditional high level synthesis to facilitate design space exploration. As technology scales to nanometer regime,...
ICCAD
2006
IEEE
14 years 7 months ago
2006
IEEE
Meeting timing constraint is one of the most important issues for modern design automation tools. This situation is exacerbated with the existence of process variation. Current hi...
VTS
2007
IEEE
14 years 5 months ago
2007
IEEE
—As the complexity of the integrated circuits increases, they become more susceptible to manufacturing faults, decreasing the total process yield. Thus, it would be desirable to ...
ASPDAC
1995
ACM
14 years 2 months ago
1995
ACM
Most existing high-level synthesis(HLS) systems attempt to generate a circuit from a behavioral description \out of the void", using the entire design space as the search dom...
ASPDAC
2008
ACM
14 years 26 days ago
2008
ACM
Abstract-- Increasing delay and power variation are significant challenges to the designers as technology scales to the deep sub-micron (DSM) regime. Traditional module selection t...