Guaranteeing performance yield in high-level synthesis

Meeting timing constraint is one of the most important issues for modern design automation tools. This situation is exacerbated with the existence of process variation. Current high-level synthesis tools, performing task scheduling, resource allocation and binding, may result in unexpected performance discrepancy due to the ignorance of the impact of process variation, which requires a shift in the design paradigm, from today’s deterministic design to statistical or probabilistic design. In this paper, we present a variation-aware performance yield-guaranteed high-level synthesis algorithm. The proposed approach integrates high-level synthesis and statistical static timing analysis into a simulated annealing engine to simultaneously explore solution space while meeting design objectives. Our results show that the area reduction is in the average of 14% when 95% performance yield is imposed with the same total completion time constraint.

• Type: Conference
• Year: 2006
• Where: ICCAD
• Authors: Wei-Lun Hung, Xiaoxia Wu, Yuan Xie
• Keywords: Completion Time Constraint, Hardware, ICCAD 2006, Statistical Static Timing, Unexpected Performance Discrepancy