112 search results - page 10 / 23 » Hardware Acceleration of Matrix Multiplication on a Xilinx F... |
FPL
2005
Springer
14 years 1 months ago
2005
Springer
Abstract. We propose CUSTARD — CUStomisable Threaded ARchitecture — a soft processor design space that combines support for multiple hardware threads and automatically generate...
ASAP
2009
IEEE
14 years 4 months ago
2009
IEEE
—This paper describes the acceleration of virtual ecology models using field-programmable gate arrays (FPGAs). Our approach targets models generated by the Virtual Ecology Workb...
ASAP
2006
IEEE
13 years 11 months ago
2006
IEEE
Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates. This paper pr...
FPGA
2003
ACM
14 years 21 days ago
2003
ACM
In this paper, we present the first exact algorithm to solve the constrained I/O placement problem for FPGAs that support multiple I/O standards. We derive a compact integer line...
PDP
2002
IEEE
14 years 12 days ago
2002
IEEE
AURA (Advanced Uncertain Reasoning Architecture) is a generic family of techniques and implementations intended for high-speed approximate search and match operations on large uns...