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ITC
2003
IEEE
92views Hardware» more  ITC 2003»
14 years 2 months ago
Infrastructure IP for Back-End Yield Improvement
The objective of this paper is to present an infrastructure IP (I-IP) designed to characterize yield loss in the process back-end. The I-IP structure is described in using a botto...
L. Forli, Jean Michel Portal, Didier Née, B...
ITC
2003
IEEE
122views Hardware» more  ITC 2003»
14 years 2 months ago
EEPROM Memory: Threshold Voltage Built In Self Diagnosis
Knowing, that the threshold voltage of the EEPROM memory cells is a key parameter to determine the overall performance of the memory, a build in structure to extract this informat...
Jean Michel Portal, Hassen Aziza, Didier Né...
ISCAS
2002
IEEE
132views Hardware» more  ISCAS 2002»
14 years 2 months ago
Lossless/lossy coding gain to evaluate coding performance of the lossless/lossy wavelet
In this report, we propose lossless/lossy coding gain as a new objective criterion to theoretically evaluate lossless and lossy coding performance of the lossless/lossy wavelet (L...
Somchart Chokchaitam, Masahiro Iwahashi
MSE
2002
IEEE
91views Hardware» more  MSE 2002»
14 years 2 months ago
A Visual Authoring Environment for Prototyping Multimedia Presentations
In this paper we describe an authoring environment which allows the author to set up and test a complex multimedia presentation by defining the synchronization relationships amon...
Ombretta Gaggi, Augusto Celentano
DATE
2000
IEEE
113views Hardware» more  DATE 2000»
14 years 2 months ago
Static Timing Analysis of Embedded Software on Advanced Processor Architectures
This paper examines several techniques for static timing analysis. In detail, the first part of the paper analyzes the connection of prediction accuracy (worst case execution tim...
André Hergenhan, Wolfgang Rosenstiel