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ASPDAC
1999
ACM
116views Hardware» more  ASPDAC 1999»
14 years 1 months ago
An Automatic Router for the Pin Grid Array Package
A Pin-Grid-Array (PGA) package router is presented in this paper. Given a chip cavity with a number of I/O pads around its boundary and an equivalent number of pins distributed on...
Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chi...
ICCAD
1999
IEEE
120views Hardware» more  ICCAD 1999»
14 years 1 months ago
Design and optimization of LC oscillators
We present a method for optimizing and automating component and transistor sizing for CMOS LC oscillators. We observe that the performance measures can be formulated as posynomial...
Maria del Mar Hershenson, Ali Hajimiri, Sunderaraj...
ACSD
1998
IEEE
101views Hardware» more  ACSD 1998»
14 years 1 months ago
A True Concurrency Semantics for ET-LOTOS
One of the central objectives of the LOTOS restandardisation activity is to de ne an enhanced LOTOS language which supports real-time speci cation. The timed extension is based up...
Howard Bowman, Joost-Pieter Katoen
ITC
1998
IEEE
61views Hardware» more  ITC 1998»
14 years 1 months ago
Test session oriented built-in self-testable data path synthesis
Existing high-level BIST synthesis methods focus on one objective, minimizing either area overhead or test time. Hence, those methods do not render exploration of large design spa...
Han Bin Kim, Takeshi Takahashi, Dong Sam Ha
ISLPED
1998
ACM
94views Hardware» more  ISLPED 1998»
14 years 1 months ago
Theoretical bounds for switching activity analysis in finite-state machines
- The objective of this paper is to provide lower and upper bounds for the switching activity on the state lines in Finite State Machines (FSMs). Using a Markov chain model for the...
Diana Marculescu, Radu Marculescu, Massoud Pedram