Sciweavers

398 search results - page 10 / 80
» Hardware Reuse at the Behavioral Level
Sort
View
ISSS
1995
IEEE
98views Hardware» more  ISSS 1995»
13 years 11 months ago
On the use of VHDL-based behavioral synthesis for telecom ASIC design
higher levels of abstraction, due to the still increasing design complexities that can be expected in the near future. Behavioral synthesis can play a key role in this prospect, as...
Mark Genoe, Paul Vanoostende, Geert van Wauwe
ISCAS
1995
IEEE
83views Hardware» more  ISCAS 1995»
13 years 11 months ago
Calculating Distortion Levels in Sampled-Data Circuits Using SPICE
This paper presents an analysis technique that can be used to compute the harmonic and intermodulation distortion levels of a sampled-data circuit directly from a SPICE transient ...
Gordon W. Roberts
DATE
2005
IEEE
90views Hardware» more  DATE 2005»
14 years 1 months ago
System Level Analysis of the Bluetooth Standard
The SystemC modules of the Link Manager Layer and Baseband Layer have been designed in this work at behavioral level to analyze the performances of the Bluetooth standard. In part...
Massimo Conti, Daniele Moretti
DAC
1999
ACM
13 years 11 months ago
Common-Case Computation: A High-Level Technique for Power and Performance Optimization
This paper presents a design methodology, called common-case computation (CCC), and new design automation algorithms for optimizing power consumption or performance. The proposed ...
Ganesh Lakshminarayana, Anand Raghunathan, Kamal S...
DATE
2003
IEEE
94views Hardware» more  DATE 2003»
14 years 20 days ago
Platform-Based Testbench Generation
This paper presents a new technology that accelerates system verification. In a real life example, we achieved a speed-up of a factor of about 5000. The key for this speed-up is a...
Renate Henftling, Andreas Zinn, Matthias Bauer, Wo...