398 search results - page 15 / 80 » Hardware Reuse at the Behavioral Level |
CGO
2008
IEEE
14 years 2 months ago
2008
IEEE
In the embedded domain, custom hardware in the form of ASICs is often used to implement critical parts of applications when performance and energy efficiency goals cannot be met ...
MICRO
2006
IEEE
14 years 2 months ago
2006
IEEE
We present and evaluate the idea of adaptive processor cache management. Specifically, we describe a novel and general scheme by which we can combine any two cache management alg...
ICTAI
2002
IEEE
14 years 1 months ago
2002
IEEE
In order to reduce the time-to-market and simplify gatelevel test generation for digital integrated circuits, GAbased functional test generation techniques are proposed for behavi...
DSD
2009
IEEE
14 years 9 days ago
2009
IEEE
Modern systems are able to put two or more processors on the same die (Chip Multiprocessors, CMP), each with its private caches, while the last level caches can be either private ...
CODES
2007
IEEE
14 years 11 days ago
2007
IEEE
Energy consumption is a major issue in dynamically reconfigurable systems because of the high power requirements during repeated configurations. Hardware designs employ low power ...