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» Hardware Reuse at the Behavioral Level
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DATE
1998
IEEE
153views Hardware» more  DATE 1998»
14 years 23 days ago
An Energy-Conscious Exploration Methodology for Reconfigurable DSPs
As the "system-on-a-chip" concept is rapidly becoming a reality, time-to-market and product complexity push the reuse of complex macromodules. Circuits combining a varie...
Jan M. Rabaey, Marlene Wan
IEEEPACT
2003
IEEE
14 years 1 months ago
Reactive Multi-Word Synchronization for Multiprocessors
Shared memory multiprocessor systems typically provide a set of hardware primitives in order to support synchronization. Generally, they provide single-word read-modify-write hard...
Phuong Hoai Ha, Philippas Tsigas
ICCAD
2001
IEEE
217views Hardware» more  ICCAD 2001»
14 years 5 months ago
ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Analog Circuits
: This paper describes ASF, a novel cell-level analog synthesis framework that can size and bias a given circuit topology subject to a set of performance objectives and a manufactu...
Michael Krasnicki, Rodney Phelps, James R. Hellums...
DATE
2007
IEEE
114views Hardware» more  DATE 2007»
14 years 2 months ago
Performance aware secure code partitioning
Many embedded applications exist where decisions are made using sensitive information. A critical issue in such applications is to ensure that data is accessed only by authorized ...
Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Ri...
ISVLSI
2007
IEEE
230views VLSI» more  ISVLSI 2007»
14 years 2 months ago
A Methodology and Toolset to Enable SystemC and VHDL Co-simulation
The new design challenges imposed by the increasing difficulties of today’s electronic systems obligated designers to develop new methodologies. System-level design and Platfor...
Richard Maciel, Bruno Albertini, Sandro Rigo, Guid...