152 search results - page 17 / 31 » Hardware Software Partitioning with Iterative Improvement He... |
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
— Memory-intensive applications present unique challenges to an ASIC designer in terms of the choice of memory organization, memory size requirements, bandwidth and access latenc...
LCTRTS
2010
Springer
13 years 5 months ago
2010
Springer
The issues of compiler optimization phase ordering and selection present important challenges to compiler developers in several domains, and in particular to the speed, code size,...
ISHPC
2003
Springer
14 years 20 days ago
2003
Springer
Simultaneous multithreaded processors use shared on-chip caches, which yield better cost-performance ratios. Sharing a cache between simultaneously executing threads causes excessi...
ISCAS
2002
IEEE
14 years 12 days ago
2002
IEEE
Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of archi...
ASPDAC
2000
ACM
13 years 12 months ago
2000
ACM
- This paper introduces the first hardwarekoftware co-synthesis algorithm that optimizes the implementations of ASICs that are used as processing elements for the embedded systems....