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136
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DAC
2004
ACM
16 years 4 months ago
Synthesizing interconnect-efficient low density parity check codes
Error correcting codes are widely used in communication and storage applications. Codec complexity has usually been measured with a software implementation in mind. A recent hardw...
Marghoob Mohiyuddin, Amit Prakash, Adnan Aziz, Way...
135
Voted
DATE
2010
IEEE
146views Hardware» more  DATE 2010»
15 years 8 months ago
Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case study
—In this paper, we examine the design process of a Network on-Chip (NoC) for a high-end commercial System onChip (SoC) application. We present several design choices and focus on...
Rudy Beraha, Isask'har Walter, Israel Cidon, Avino...
143
Voted
CODES
2008
IEEE
15 years 10 months ago
Static analysis of processor stall cycle aggregation
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
Jongeun Lee, Aviral Shrivastava
101
Voted
BIOADIT
2006
Springer
15 years 7 months ago
MOVE Processors That Self-replicate and Differentiate
Abstract. This article describes an implementation of a basic multiprocessor system that exhibits replication and differentiation abilities on the POEtic tissue, a programmable har...
Joël Rossier, Yann Thoma, Pierre-André...
134
Voted
ICCD
2001
IEEE
110views Hardware» more  ICCD 2001»
16 years 18 days ago
Low-Energy DSP Code Generation Using a Genetic Algorithm
This paper deals with low-energy code generation for a highly optimized digital signal processor designed for mobile communication applications. We present a genetic algorithm bas...
Markus Lorenz, Rainer Leupers, Peter Marwedel, Tho...