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ASAP
2003
IEEE
153views Hardware» more  ASAP 2003»
14 years 4 months ago
Hardware Synthesis for Multi-Dimensional Time
This paper introduces basic principles for extending the classical systolic synthesis methodology to multi-dimensional time. Multi-dimensional scheduling enables complex algorithm...
Anne-Claire Guillou, Patrice Quinton, Tanguy Risse...
ARC
2008
Springer
104views Hardware» more  ARC 2008»
14 years 26 days ago
PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications
Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications....
Frank Hannig, Holger Ruckdeschel, Hritam Dutta, J&...
ASYNC
2005
IEEE
132views Hardware» more  ASYNC 2005»
14 years 4 months ago
High Level Synthesis of Timed Asynchronous Circuits
This paper proposes applying a logic synthesis approach to high level synthesis from SpecC specifications to timed asynchronous gate-level circuits. The state-based logic synthes...
Tomohiro Yoneda, Atsushi Matsumoto, Manabu Kato, C...
ICCD
1993
IEEE
84views Hardware» more  ICCD 1993»
14 years 3 months ago
Fast Timing Analysis for Hardware-Software Co-Synthesis
W. Ye, Rolf Ernst, Thomas Benner, Jörg Henkel
ISSS
1999
IEEE
112views Hardware» more  ISSS 1999»
14 years 3 months ago
Middleware Techniques and Optimizations for Real-Time, Embedded Systems
ended tutorial abstract appeared in the Proceedings of the 12th International Symposium On System Synthesis, IEEE, San Jose, CA, USA November, 11, 1999.
Douglas C. Schmidt