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106
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FPL
2000
Springer
103views Hardware» more  FPL 2000»
15 years 7 months ago
Evaluation of Accelerator Designs for Subgraph Isomorphism Problem
Many applications can be modeled as subgraph isomorphism problems. However, this problem is generally NP-complete and difficult to compute. A custom computing circuit is a prospect...
Shuichi Ichikawa, Hidemitsu Saito, Lerdtanaseangth...
113
Voted
DRM
2004
Springer
15 years 9 months ago
Attacks and risk analysis for hardware supported software copy protection systems
Recently, there is a growing interest in the research community to use tamper-resistant processors for software copy protection. Many of these tamper-resistant systems rely on a s...
Weidong Shi, Hsien-Hsin S. Lee, Chenghuai Lu, Tao ...
121
Voted
ICCAD
1994
IEEE
104views Hardware» more  ICCAD 1994»
15 years 7 months ago
Module selection and data format conversion for cost-optimal DSP synthesis
In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear p...
Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi
116
Voted
ISSS
1995
IEEE
109views Hardware» more  ISSS 1995»
15 years 7 months ago
1995 high level synthesis design repository
In this paper we brie y describe a set of designs that can serve as examples for High Level Synthesis (HLS) systems. The designs vary in complexity from simple behavioral nite st...
Preeti Ranjan Panda, Nikil D. Dutt
128
Voted
ICCD
2006
IEEE
182views Hardware» more  ICCD 2006»
16 years 14 days ago
A performance and power analysis of WK-Recursive and Mesh Networks for Network-on-Chips
—Network-on-Chip (NoC) has been proposed as an attractive alternative to traditional dedicated wires to achieve high performance and modularity. Power efficiency is one of the mo...
Dara Rahmati, Abbas Eslami Kiasari, Shaahin Hessab...