Sciweavers

3902 search results - page 140 / 781
» Hardware Synthesis from C C Models
Sort
View
SASP
2009
IEEE
291views Hardware» more  SASP 2009»
15 years 10 months ago
FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs
— As growing power dissipation and thermal effects disrupted the rising clock frequency trend and threatened to annul Moore’s law, the computing industry has switched its route...
Alexandros Papakonstantinou, Karthik Gururaj, John...
ISQED
2007
IEEE
206views Hardware» more  ISQED 2007»
15 years 10 months ago
Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations
Abstract—A Network-on-Chip (NoC) replaces on-chip communication implemented by point-to-point interconnects in a multi-core environment by a set of shared interconnects connected...
Mosin Mondal, Tamer Ragheb, Xiang Wu, Adnan Aziz, ...
104
Voted
DATE
2010
IEEE
146views Hardware» more  DATE 2010»
15 years 3 months ago
Automatic pipelining from transactional datapath specifications
Abstract—We present a transactional datapath specification (Tspec) and the tool (T-piper) to synthesize automatically an inpelined implementation from it. T-spec abstractly views...
Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-...
124
Voted
ASPDAC
2004
ACM
126views Hardware» more  ASPDAC 2004»
15 years 9 months ago
High-level area and power-up current estimation considering rich cell library
— Reducing the ever-growing leakage power is critical to power efficient designs. Leakage reduction techniques such as power-gating using sleep transistor insertion introduces la...
Fei Li, Lei He, Joseph M. Basile, Rakesh J. Patel,...
113
Voted
ICCD
2008
IEEE
122views Hardware» more  ICCD 2008»
16 years 17 days ago
Acquiring an exhaustive, continuous and real-time trace from SoCs
— The amount of time and resources that have to be spent on debugging of embedded cores continuously increases. Approaches valid 10 years ago can no longer be used due to the var...
Christian Hochberger, Alexander Weiss