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» Hardware design experiences in ZebraNet
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FPGA
2007
ACM
150views FPGA» more  FPGA 2007»
14 years 4 months ago
FPGA-friendly code compression for horizontal microcoded custom IPs
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
Bita Gorjiara, Daniel Gajski
DATE
2006
IEEE
113views Hardware» more  DATE 2006»
14 years 4 months ago
Automatic ADL-based operand isolation for embedded processors
Cutting-edge applications of future embedded systems demand highest processor performance with low power consumption to get acceptable battery-life times. Therefore, low power opt...
Anupam Chattopadhyay, B. Geukes, David Kammler, Er...
CASES
2007
ACM
14 years 2 months ago
Eliminating inter-process cache interference through cache reconfigurability for real-time and low-power embedded multi-tasking
We propose a technique which leverages configurable data caches to address the problem of cache interference in multitasking embedded systems. Data caches are often necessary to p...
Rakesh Reddy, Peter Petrov
ADBIS
1995
Springer
155views Database» more  ADBIS 1995»
14 years 1 months ago
The MaStA I/O Cost Model and its Validation Strategy
Crash recovery in database systems aims to provide an acceptable level of protection from failure at a given engineering cost. A large number of recovery mechanisms are known, and...
S. Scheuerl, Richard C. H. Connor, Ronald Morrison...
ASPLOS
2010
ACM
14 years 1 months ago
Orthrus: efficient software integrity protection on multi-cores
This paper proposes an efficient hardware/software system that significantly enhances software security through diversified replication on multi-cores. Recent studies show that a ...
Ruirui Huang, Daniel Y. Deng, G. Edward Suh