951 search results - page 56 / 191 » Hardware design experiences in ZebraNet |
VTS
1999
IEEE
13 years 12 months ago
1999
IEEE
High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test patte...
ITC
1998
IEEE
13 years 12 months ago
1998
IEEE
Previously-proposed strategies for VLSI fault diagnosis have su ered from a variety of self-imposed limitations. Some techniques are limited to a speci c fault model, and many wil...
ASPDAC
1998
ACM
13 years 12 months ago
1998
ACM
- In this paper, we study the wire sizing and wire spacing problem for post-layout performance optimization under Elmore delay model. Both ground capacitance and coupled capacitanc...
ICCAD
1996
IEEE
13 years 12 months ago
1996
IEEE
State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (flip-flops)...
ICCAD
1996
IEEE
13 years 12 months ago
1996
IEEE
In this paper we present an ecient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations con...