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» Hardware support for code integrity in embedded processors
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ISCA
2000
IEEE
134views Hardware» more  ISCA 2000»
13 years 12 months ago
Architectural support for scalable speculative parallelization in shared-memory multiprocessors
Speculative parallelization aggressively executes in parallel codes that cannot be fully parallelized by the compiler. Past proposals of hardware schemes have mostly focused on si...
Marcelo H. Cintra, José F. Martínez,...
TVLSI
2002
94views more  TVLSI 2002»
13 years 7 months ago
A network flow approach to memory bandwidth utilization in embedded DSP core processors
This paper presents a network flow approach to solving the register binding and allocation problem for multiword memory access DSP processors. In recently announced DSP processors,...
Catherine H. Gebotys
DATE
2004
IEEE
122views Hardware» more  DATE 2004»
13 years 11 months ago
Phase Coupled Code Generation for DSPs Using a Genetic Algorithm
The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting special hardware features. Due to the irregular arc...
Markus Lorenz, Peter Marwedel
DATE
2003
IEEE
92views Hardware» more  DATE 2003»
14 years 24 days ago
An Integrated Approach for Improving Cache Behavior
The widening gap between processor and memory speeds renders data locality optimization a very important issue in data-intensive embedded applications. Throughout the years hardwa...
Gokhan Memik, Mahmut T. Kandemir, Alok N. Choudhar...
FPL
2006
Springer
242views Hardware» more  FPL 2006»
13 years 11 months ago
TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs
With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...
Manuel Saldaña, Paul Chow