43 search results - page 4 / 9 » Hiding Cache Miss Penalty Using Priority-based Execution for... |
DAC
2003
ACM
14 years 8 months ago
2003
ACM
Schedulability analysis of real-time embedded systems requires worst case timing guarantees of embedded software performance. This involves not only language level program analysi...
RTAS
1997
IEEE
13 years 11 months ago
1997
IEEE
3rd IEEE Real-time Technology and Applications Symposium (RTAS), June 1997 in Montreal, Canada Cache-partitioning techniques have been invented to make modern processors with an e...
RTAS
2005
IEEE
14 years 1 months ago
2005
IEEE
While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
RTAS
2008
IEEE
14 years 2 months ago
2008
IEEE
Multi-core chips have been increasingly adopted by microprocessor industry. For real-time systems to safely harness the potential of multi-core computing, designers must be able t...
ASPLOS
1992
ACM
13 years 11 months ago
1992
ACM
Software-controlled data prefetching is a promising technique for improving the performance of the memory subsystem to match today's high-performance processors. While prefet...