238 search results - page 21 / 48 » Hierarchical Interconnect Circuit Models |
ICCAD
1997
IEEE
13 years 11 months ago
1997
IEEE
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
— Statistical static timing analysis deals with the increasing variations in manufacturing processes to reduce the pessimism in the worst case timing analysis. Because of the cor...
WSC
2004
13 years 9 months ago
2004
HDPS is a practical system for designing modeling paradigms, creating hierarchal model definitions, and evaluating multi-paradigm models - particularly in business and finance. HD...
3DIC
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—Modeling parasitic parameters of Through-SiliconVia (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circ...
DAC
2000
ACM
14 years 8 months ago
2000
ACM
The effect of crosstalk errors is most significant in highperformance circuits, mandating at-speed testing for crosstalk defects. This paper describes a self-test methodology that...