238 search results - page 37 / 48 » Hierarchical Interconnect Circuit Models |
DAC
1997
ACM
13 years 12 months ago
1997
ACM
We present a novel technique CLIP for optimizing both the height and width of CMOS cell layouts in the two-dimensional (2D) style. CLIP is based on integer-linear programming (ILP...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Process variations in modern VLSI technologies are growing in both magnitude and dimensionality. To assess performance variability, complex simulation and performance models param...
ASPDAC
2009
ACM
2009
ACM
Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture
13 years 11 months ago
-- Carbon nanotubes (CNTs) and carbon nanotube field effect transistors (CNFETs) have demonstrated extraordinary properties and are widely accepted as the building blocks of next g...
VLSID
2004
IEEE
14 years 8 months ago
2004
IEEE
Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
Extracting the inductance of complex interconnect topologies is a formidable task, and simulating the resulting dense partial inductance matrix is even more difficult. Furthermore...