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DAC
2008
ACM
14 years 8 months ago
Driver waveform computation for timing analysis with multiple voltage threshold driver models
This paper introduces an accurate and efficient electrical analysis of logic gates modeled as Multiple Voltage Threshold Models (MVTM) loaded by the associated interconnect. MVTMs...
Peter Feldmann, Soroush Abbaspour, Debjit Sinha, G...
ISCAS
2005
IEEE
130views Hardware» more  ISCAS 2005»
14 years 1 months ago
RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction
Inductance effects of on-chip interconnects have become more and more significant in today’s high-speed digital circuits, especially for global interconnects such as signal buse...
Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang
FPGA
1999
ACM
142views FPGA» more  FPGA 1999»
13 years 12 months ago
Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems
Multi-FPGA systems are used as custom computing machines to solve compute intensive problems and also in the verification and prototyping of large circuits. In this paper, we addr...
Abdel Ejnioui, N. Ranganathan
CSUR
2006
147views more  CSUR 2006»
13 years 7 months ago
A survey of research and practices of Network-on-chip
resents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. ...
Tobias Bjerregaard, Shankar Mahadevan
DAC
1998
ACM
14 years 8 months ago
Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs
In this paper we present a new global router appropriate for Multichip Module MCM and dense Printed Circuit Board PCB design, which utilizes a hybrid of the classical rip-up and r...
Jason Cong, Patrick H. Madden