251 search results - page 33 / 51 » Hierarchical Modeling and Simulation of Large Analog Circuit... |
VLSID
2001
IEEE
14 years 8 months ago
2001
IEEE
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
Abstract - Today's digital design systems are running out of steam, when it comes to meeting the challenges presented by simultaneous switching, power consumption and reliabil...
SADM
2010
13 years 2 months ago
2010
This paper is concerned with classifying high dimensional data into one of two categories. In various settings, such as when dealing with fMRI and microarray data, the number of v...
ISQED
2006
IEEE
14 years 1 months ago
2006
IEEE
— In this paper, we propose an efficient model order reduction (MOR) algorithm, called MTermMOR, for modeling interconnect circuits with large number of external ports. The prop...
DATE
2000
IEEE
14 years 1 days ago
2000
IEEE
A novel method which can be regarded as the noisecounterpart of the celebrated Elmore’s delay formula— both being based on the first two moments of the network’s transfer fu...