249 search results - page 12 / 50 » High Level Synthesis of Timed Asynchronous Circuits |
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
Importance of addressing soft errors in both safety critical applications and commercial consumer products is increasing, mainly due to ever shrinking geometries, higher-density c...
DSD
2010
IEEE
13 years 5 months ago
2010
IEEE
Asynchronous circuit implementations operating under strong constraints (DIMS, Direct Logic, some of NCL gates, etc.) are attractive due to: 1) regularity; 2) combined implementati...
ISQED
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract — Nanoelectronic design faces unprecedented reliability challenges and must achieve noise immunity and delay insensitiveness in the presence of prevalent defects and sig...
DELTA
2006
IEEE
13 years 11 months ago
2006
IEEE
The difficulties of designing nanoscale circuits include the need for regular circuit structure and controlling the timing requirements. A cellular array has highly regular struct...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
The use of nanometer technologies is making it increasingly important to consider transient characteristics of a circuit’s power dissipation (e.g., peak power, and power gradien...