249 search results - page 32 / 50 » High Level Synthesis of Timed Asynchronous Circuits |
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
DAC
2010
ACM
13 years 6 months ago
2010
ACM
As high-level models in C and SystemC are increasingly used for verification and even design (through high-level synthesis) of electronic systems, there is a growing need for com...
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
- This paper addresses the problem of true delay estimation during high level design. The existing delay estimation techniques either estimate the topological delay of the circuit ...
DATE
2003
IEEE
14 years 29 days ago
2003
IEEE
: Over the years, many design methodologies/tools and layout architectures have been developed for datapath-oriented designs. One commonly used approach for high-speed datapath des...
HPCA
1998
IEEE
13 years 11 months ago
1998
IEEE
The counterflow pipeline concept was originated by Sproull et al.[1] to demonstrate the concept of asynchronous circuits. This architecture relies on distributed decision making an...