80 search results - page 4 / 16 » High level synthesis for reconfigurable datapath structures |
DATE
1998
IEEE
14 years 6 days ago
1998
IEEE
This paper presents a new approach to cross-level hierarchical high-level synthesis. A methodology is presented, that supports the efficient synthesis of hierarchical specified sy...
ASPDAC
1995
ACM
13 years 11 months ago
1995
ACM
- In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm a...
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
TRETS
2010
13 years 6 months ago
2010
s, and abstractions, typically enabling faster development times than with traditional Hardware ion Languages (HDLs). However, programming at a higher level of abstraction is typic...
ICCAD
1990
IEEE
14 years 1 hour ago
1990
IEEE
