80 search results - page 5 / 16 » High level synthesis for reconfigurable datapath structures |
DATE
2003
IEEE
14 years 1 months ago
2003
IEEE
: Over the years, many design methodologies/tools and layout architectures have been developed for datapath-oriented designs. One commonly used approach for high-speed datapath des...
DAC
2012
ACM
11 years 10 months ago
2012
ACM
In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...
VLSID
2003
IEEE
14 years 8 months ago
2003
IEEE
The design of modern complex embedded systems require a high level of abstraction of the design. The SimnML[1] is a specification language to model processors for such designs. Se...
ICCD
2001
IEEE
14 years 4 months ago
2001
IEEE
In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and ...
ISSS
1995
IEEE
13 years 11 months ago
1995
IEEE
We present an integrated approach aimed at predicting layout area needed to implement a behavioral description for a given performance goal. Our approach is novel because: (1) it ...