Sciweavers

18572 search results - page 3538 / 3715
» High performance C
Sort
View
ICCD
2006
IEEE
148views Hardware» more  ICCD 2006»
14 years 6 months ago
Trends and Future Directions in Nano Structure Based Computing and Fabrication
— As silicon CMOS devices are scaled down into the nanoscale regime, new challenges at both the device and system level are arising. While some of these challenges will be overco...
R. Iris Bahar
ICCD
2003
IEEE
137views Hardware» more  ICCD 2003»
14 years 6 months ago
Dynamic Thread Resizing for Speculative Multithreaded Processors
There is a growing interest in the use of speculative multithreading to speed up the execution of a program. In speculative multithreading model, threads are extracted from a sequ...
Mohamed M. Zahran, Manoj Franklin
ICCAD
2008
IEEE
170views Hardware» more  ICCAD 2008»
14 years 6 months ago
A polynomial time approximation scheme for timing constrained minimum cost layer assignment
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...
Shiyan Hu, Zhuo Li, Charles J. Alpert
ICCAD
2007
IEEE
98views Hardware» more  ICCAD 2007»
14 years 6 months ago
Device-circuit co-optimization for mixed-mode circuit design via geometric programming
Modern processing technologies offer a number of types of devices such as high-VT , low-VT , thick-oxide, etc. in addition to the nominal transistor in order to meet system perfor...
Jintae Kim, Ritesh Jhaveri, Jason Woo, Chih-Kong K...
ICCAD
2006
IEEE
117views Hardware» more  ICCAD 2006»
14 years 6 months ago
Post-routing redundant via insertion and line end extension with via density consideration
- Redundant via insertion and line end extension employed in the post-routing stage are two well known and highly recommended techniques to reduce yield loss due to via failure. Ho...
Kuang-Yao Lee, Ting-Chi Wang, Kai-Yuan Chao
« Prev « First page 3538 / 3715 Last » Next »