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INFOCOM
1995
IEEE
13 years 11 months ago
A Fast Bypass Algorithm for High-Speed Networks
In this work we suggest an algorithm that increases the reservation success probability for bursty tra c in high speed networks by adding exibility to the construction of the rout...
Israel Cidon, Raphael Rom, Yuval Shavitt
ICCD
2001
IEEE
213views Hardware» more  ICCD 2001»
14 years 4 months ago
Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI Circuits
Abstract-- Scaling the minimum feature size of VLSI circuits to sub-quarter micron and its clock frequency to 2GHz has caused crosstalk noise to become a serious problem, that degr...
Payam Heydari, Massoud Pedram
DATE
2003
IEEE
131views Hardware» more  DATE 2003»
14 years 27 days ago
High Speed and Highly Testable Parallel Two-Rail Code Checker
In this article we propose a high speed and highly testable parallel two-rail code checker, which features a compact structure and is Totally-Self-Checking or Strongly Code-Disjoi...
Martin Omaña, Daniele Rossi, Cecilia Metra
HIPEAC
2010
Springer
14 years 4 months ago
Low-Overhead, High-Speed Multi-core Barrier Synchronization
Whereas efficient barrier implementations were once a concern only in high-performance computing, recent trends in core integration make the topic relevant even for general-purpos...
John Sartori, Rakesh Kumar
ICCD
2006
IEEE
77views Hardware» more  ICCD 2006»
14 years 4 months ago
Iterative-Constructive Standard Cell Placer for High Speed and Low Power
Abstract— Timing and low power emerge as the most important goals in contemporary design. Meanwhile, the majority of placement algorithms developed by industry and academia still...
Sungjae Kim, Eugene Shragowitz