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DATE
2008
IEEE
99views Hardware» more  DATE 2008»
14 years 2 months ago
GMDS: Hardware implementation of novel real output queuing architecture
In this paper, a real output queuing switch prototype implementation is presented. This implementation is based on a novel high speed multidrop backplane and a general purpose lin...
R. Arteaga, Félix Tobajas, Roberto Esper-Ch...
ITC
1998
IEEE
69views Hardware» more  ITC 1998»
13 years 11 months ago
A performance analysis system for MEMS using automated imaging methods
The ability to make in-situ performance measurements of MEMS operating at high speeds has been demonstrated using a new image analysis system. Significant improvements in performa...
Glenn F. LaVigne, Sam L. Miller
ICCD
1997
IEEE
87views Hardware» more  ICCD 1997»
13 years 11 months ago
Synthesizing Iterative Functions into Delay-Insensitive Tree Circuits
Speed, cost and correctness may be the most important factors in designing a digital system. This paper proposes a novel and general methodology to synthesize iterative functions ...
Fu-Chiung Cheng
ISLPED
1996
ACM
72views Hardware» more  ISLPED 1996»
13 years 11 months ago
Energy recovery for the design of high-speed, low-power static RAMs
We present a low-power SRAM design based on the theory of energy recovery that reduces the dissipation associated with write operations while operating at high speed. The energy-r...
Nestoras Tzartzanis, William C. Athas
SIGIR
2003
ACM
14 years 24 days ago
HAT: a hardware assisted TOP-DOC inverted index component
A novel Hardware Assisted Top-Doc (HAT) component is disclosed. HAT is an optimized content indexing device based on a modified inverted index structure. HAT accommodates patterns...
S. Kagan Agun, Ophir Frieder