290 search results - page 33 / 58 » High-Speed MARS Hardware |
ITC
1998
IEEE
13 years 11 months ago
1998
IEEE
New methodologies based on functional testing and built-in self-test can narrow the gap between necessary solutions and existing techniques for processor validation and testing. W...
FPL
1998
Springer
13 years 11 months ago
1998
Springer
This paper discusses the memory interface of custom computing machines. We present a high speed parallel memory for the MoM-PDA machine, which is based on the Xputer paradigm. The ...
ASAP
1996
IEEE
13 years 11 months ago
1996
IEEE
A datapath synthesis system (DPSS) for a bus-based wavefront array architecture, called rDPA (reconfigurable datapath architecture), is presented. An internal data bus to the arra...
ASPDAC
1995
ACM
13 years 11 months ago
1995
ACM
Abstract — A datapath synthesis system (DPSS) for the reconfigurable datapath architecture (rDPA) is presented. The DPSS allows automatic mapping of high level descriptions onto...
MSS
1995
IEEE
13 years 11 months ago
1995
IEEE
This paper will attempt to examine the industry requirements for shared network data storage and sustained high speed (10’s to 100’s to thousands of megabytes per second) netw...