140 search results - page 19 / 28 » High-level design for asynchronous logic |
ISPD
2012
ACM
12 years 3 months ago
2012
ACM
There are two prominent problems with technology scaling: increasing design complexity and more challenges with interconnect design, including routability. High-level synthesis ha...
ENTCS
2006
13 years 7 months ago
2006
Klaim is an experimental language designed for modeling and programming distributed systems composed of mobile components where distribution awareness and dynamic system architect...
DATE
2002
IEEE
14 years 16 days ago
2002
IEEE
Phased logic has been proposed as a technique for realizing self-timed circuitry that is delay-insensitive and requires no global clock signals. Early evaluation techniques have b...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
This paper addresses the problem of computational error modeling and analysis. Choosing different word-lengths for each functional unit in hardware implementations of numerical al...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
We address the problem of estimating controller delay from high-level specifications during behavioral synthesis. Typically, the critical path of a synthesised behavioral design g...