121 search results - page 11 / 25 » Hybrid cache architecture with disparate memory technologies |
ICCD
2008
IEEE
14 years 3 months ago
2008
IEEE
— We use a novel virtualization-based approach for computer architecture performance analysis. We present a case study analyzing a hypothetical hybrid main memory, which consists...
ICCD
2006
IEEE
14 years 3 months ago
2006
IEEE
Abstract— The continuing divergence of processor and memory speeds has led to the increasing reliance on larger caches which have become major consumers of area and power in embe...
HIPC
1999
Springer
13 years 11 months ago
1999
Springer
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...
MICRO
2009
IEEE
14 years 1 months ago
2009
IEEE
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...
SC
2000
ACM
13 years 11 months ago
2000
ACM
The current trend in HPC hardware is towards clusters of shared-memory (SMP) compute nodes. For applications developers the major question is how best to program these SMP cluster...