121 search results - page 19 / 25 » Hybrid cache architecture with disparate memory technologies |
SOSP
2009
ACM
14 years 4 months ago
2009
ACM
Modern computer systems have been built around the assumption that persistent storage is accessed via a slow, block-based interface. However, new byte-addressable, persistent memo...
HPCA
2009
IEEE
14 years 7 months ago
2009
IEEE
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
ISCA
2010
IEEE
14 years 12 days ago
2010
IEEE
DRAM vendors have traditionally optimized the cost-perbit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, wher...
MICRO
2003
IEEE
14 years 18 days ago
2003
IEEE
Wire delays are a major concern for current and forthcoming processors. One approach to attack this problem is to divide the processor into semi-independent units referred to as c...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die ...