128 search results - page 3 / 26 » ILP-based optimization of sequential circuits for low power |
IWSOC
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper explores the design and optimization of Quasi-Floating Gate MOS techniques to lowvoltage/low-power digital circuitry. The simulated power consumption of standard CMOS g...
DAC
1996
ACM
13 years 11 months ago
1996
ACM
Recent trends in the semiconductor industry have resulted in an increasing demand for low power circuits. POSE is a step in providing the EDA community and academia with an enviro...
ISCAS
2002
IEEE
14 years 11 days ago
2002
IEEE
A technique for computing the switching activity of synchronous Finite State Machine (FSM) implementations including the influence of temporal correlation among the next state si...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
This paper attempts to determine the capabilities of existing Redundancy Addition and Removal (SRAR) techniques for logic optimization of sequential circuits. To this purpose, we ...
DAC
1995
ACM
13 years 11 months ago
1995
ACM
—We survey state-of-the-art optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are cons...