This paper presents a methodology for the statistical analysis of clock tree structures. It allows to accurately predict and analyze the impact of process variation on clock skew....
Enrico Malavasi, Stefano Zanella, Min Cao, Julian ...
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Abstract-- Nanometer VLSI systems demand robust clock distribution network design for increased process and operating condition variabilities. In this paper, we propose minimum clo...
Bao Liu, Andrew B. Kahng, Xu Xu, Jiang Hu, Ganesh ...
This paper discusses clock skew due to manufacturing variability and environmental change. In clock tree design, transition time constraint is an important design parameter that c...
Influence of manufacturing variability on circuit performance has been increasing because of finer manufacturing process and lowered supply voltage. In this paper, we focus on m...