305 search results - page 20 / 61 » Impact of Parallel Workloads on NoC Architecture Design |
129
Voted
MICRO
2006
IEEE
15 years 11 months ago
2006
IEEE
Recently-proposed processor microarchitectures for high Memory Level Parallelism (MLP) promise substantial performance gains. Unfortunately, current cache hierarchies have Miss-Ha...
159
Voted
ISCA
2011
IEEE
14 years 9 months ago
2011
IEEE
Optimizing the performance of a multi-core microprocessor within a power budget has recently received a lot of attention. However, most existing solutions are centralized and cann...
159
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HPCA
2009
IEEE
16 years 6 months ago
2009
IEEE
Previous studies have proposed techniques to dynamically change the architecture of a processor to better suit the characteristics of the workload at hand. However, all such appro...
168
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TPDS
2002
15 years 5 months ago
2002
Middleware has been introduced to provide interoperability as well as transparent location of servers in heterogeneous client-server environments. Although such benefits accrue fro...
148
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DAC
2008
ACM
16 years 6 months ago
2008
ACM
An energy optimization is proposed that addresses the nontrivial digital contribution to power and impact on performance in high-speed mixed-signal circuits. Parallel energy and b...