5562 search results - page 1062 / 1113 » Implementing Parallel Cell-DEVS |
HPCA
2007
IEEE
14 years 9 months ago
2007
IEEE
3D integration technology greatly increases transistor density while providing faster on-chip communication. 3D implementations of processors can simultaneously provide both laten...
HPCA
2007
IEEE
14 years 9 months ago
2007
IEEE
This paper proposes a hardware transactional memory (HTM) system called LogTM Signature Edition (LogTM-SE). LogTM-SE uses signatures to summarize a transaction's readand writ...
HPCA
2006
IEEE
14 years 9 months ago
2006
IEEE
An important means of validating the design of commercial-grade shared memory multiprocessors is to run a large number of pseudo-random test programs on them. However, when intent...
HPCA
2005
IEEE
14 years 9 months ago
2005
IEEE
This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a Chip Multi-Processor (CMP) architecture. Cache sharing impacts threads non-u...
HPCA
2005
IEEE
14 years 9 months ago
2005
IEEE
Long-latency loads are critical in today's processors due to the ever-increasing speed gap with memory. Not only do these loads block the execution of dependent instructions,...