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» Implementing a STARI chip
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FPL
2010
Springer
170views Hardware» more  FPL 2010»
13 years 7 months ago
IP Based Configurable SIMD Massively Parallel SoC
Significant advances in the field of configurable computing have enabled parallel processing within a single FieldProgrammable Gate Array (FPGA) chip. This paper presents the imple...
Mouna Baklouti, Mohamed Abid, Philippe Marquet, Je...
MICRO
2008
IEEE
137views Hardware» more  MICRO 2008»
13 years 9 months ago
Verification of chip multiprocessor memory systems using a relaxed scoreboard
Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to ...
Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin...
VLSID
2005
IEEE
117views VLSI» more  VLSID 2005»
14 years 10 months ago
On-Chip Voltage Regulator with Improved Transient Response
A new technique has been proposed to improve the transient behavior of the on-chip/embedded voltage regulator. It is realized by introducing a dynamic leakage path at the driver s...
Ashis Maity, R. G. Raghavendra, Pradip Mandal
ASPDAC
2007
ACM
133views Hardware» more  ASPDAC 2007»
14 years 1 months ago
RTOS and Codesign Toolkit for Multiprocessor Systems-on-Chip
Abstract-- Multiprocessor designs have become popular in embedded domains for achieving the power and performance requirements. In this paper, we present principles and techniques ...
Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
DATE
2008
IEEE
113views Hardware» more  DATE 2008»
13 years 11 months ago
Run-time Spatial Mapping of Streaming Applications to a Heterogeneous Multi-Processor System-on-Chip (MPSOC)
In this paper, the problem of spatial mapping is defined. Reasons are presented to show why performing spatial mappings at run-time is both necessary and desirable and criteria fo...
Philip K. F. Hölzenspies, Johann Hurink, Jan ...