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» Implementing a STARI chip
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DATE
2007
IEEE
109views Hardware» more  DATE 2007»
14 years 4 months ago
Toward a scalable test methodology for 2D-mesh Network-on-Chips
1 This paper presents a BIST strategy for testing the NoC interconnect network, and investigates if the strategy is a suitable approach for the task. All switches and links in the ...
Kim Petersén, Johnny Öberg
DDECS
2007
IEEE
80views Hardware» more  DDECS 2007»
14 years 4 months ago
Design Platform for Quick Integration of an Internet Connectivity into System-on-Chips
— The paper describes pre-integrated subsystem consisting of a configurable 8-bit microcontroller and an Internet connection solution. The latter integrates Ethernet Media Access...
Bartosz Wojciechowski, Tomasz Kowalczyk, Wojciech ...
ETS
2006
IEEE
113views Hardware» more  ETS 2006»
14 years 3 months ago
Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism
This paper proposes a wrapper design for interconnects with guaranteed bandwidth and latency services and on-chip protocol. strate that these interconnects abstract the interconne...
Alexandre M. Amory, Kees Goossens, Erik Jan Marini...
PERVASIVE
2004
Springer
14 years 3 months ago
Ubiquitous Chip: A Rule-Based I/O Control Device for Ubiquitous Computing
In this paper, we propose a new framework for ubiquitous computing by rule-based, event-driven I/O (input/output) control devices. Our approach is flexible and autonomous because ...
Tsutomu Terada, Masahiko Tsukamoto, Keisuke Hayaka...
ITC
2003
IEEE
145views Hardware» more  ITC 2003»
14 years 3 months ago
CHARDIN: An Off-Chip Transient Current Monitor with Digital Interface for Production Testing
We present a measurement module that computes the charge from the transient supply current and provides a digital value of this magnitude. The module is constructed to provide a f...
Bartomeu Alorda, B. Bloechel, Ali Keshavarzi, Jaum...